1 of 9 092399 features low-power cmos design standby current - 50 na max at t a = 25c v cc = 3.0v - 100 na max at t a = 25c v cc = 5.5v - 1 a max at t a = 60c v cc = 5.5v full operation for v cc = 5.5v to 2.7v data retention voltage = 5.5v to 2.0v fast 5v access time - ds2016 - 100 100 ns - ds2016 - 150 150 ns reduced-speed 3v access time - ds2016 - 100 250 ns - ds2016 - 150 250 ns operating temperature range of -40c to +85c full static operation ttl compatible inputs and outputs over voltage range of 5.5v to 2.7 volts. available in 24-pin dip and 24-pin soic packages suitable for both battery operated and battery backup applications pin assignment pin description a0 - a10 - address inputs dq0 - dq7 - data input/output ce - ch ip enable input we - write enable input oe - output enable input v cc - power supply input 2.7v - 5.5v gnd - ground description the ds2016 2k x 8 3v/5v operation static ram is a 16,384-bit, low-power, fully static random access memory organized as 2048 words by 8 bits using cmos technology. the device operates from a single power supply with a voltage input between 2.7 and 5.5 volts. the chip enable input ( ce ) is used for device selection and can be used in order to achieve the minimum standby current mode, which facilitates both battery operated and battery backup applications. the device provides access times as fast as 100 ns when operated from a 5-volt power supply input and also provides relatively good performance of 250 ns access while operating from a 3-volt input. the device maintains ttl-level inputs and outputs over the input voltage range of 2.7 to 5.5 volts. the ds2016 is most suitable for low-power applications where battery operation or battery backup for nonvolatility is required. the ds2016 is a jedec-standard 2k x 8 sram and is pin-compatible with rom and eprom of similar density. ds2016 2k x 8 3v/5v operation static ram www.dalsemi.com 1 2 3 4 5 6 7 8 9 10 11 12 13 24 23 22 21 20 19 18 17 16 15 14 v cc a8 a9 we oe a10 ce dq7 dq6 dq5 dq4 dq3 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd ds2016 24-pin dip (600-mil) ds2016r 24-pin soic (300-mil)
ds2016 2 of 9 operation mode mode ce oe we a0-a10 dq-dq7 power read l l h stable data out i cco write l x l stable data in i cco deselect l h h x high-z i cco standby h x x x high-z i ccs absolute maximum ratings symbol parameter rating v cc power supply voltage -0.3v to +7.0v v in , v i/o input, input/output voltage -0.3 to v cc +0.3v t stg storage temperature -55 c to +125 c t opr operating temperature -40 c to +85 c t solder soldering temperature/time 260 c for 10 seconds capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf +5-volt operation recommended dc operating conditions (t a = -40 c to +85 c) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.0 v cc +0.3 v input low voltage v il -0.3 0.8 v data retention voltage v dr 2.0 5.5 v dc characteristics (t a = -40 c to +85 c; v cc = 5v 10%) parameter symbol conditions min typ max units input leakage current i il 0v v in v cc 0.1 a i/o leakage current i lo ce = v ih , 0v v io v cc 0.5 a output high current i oh v oh = 2.4v -1.0 ma output low current i ol v ol = 0.4v 4.0 ma standby current i ccs1 ce = 2.0v 0.3 ma standby current i ccs2 ce 3 v cc -0.5v t a =60c 1 a standby current i ccs2 ce 3 v cc -0.5v t a =25c 100 na operating current i cco ce = 0.8v, 200 ns cycle 55 ma
ds2016 3 of 9 ac characteristics read cycle (t a = -40 c to +85 c; v cc = 5v 10%) ds2016-100 DS2016-150 parameter symbol min typ max min typ max units notes read cycle time t rc 100 150 ns access time t acc 100 150 ns oe to output valid t oe 50 70 ns ce to output valid t co 100 150 ns ce or oe to output active t coe 5 5 ns output high-z from deselection t od 5 35 10 60 ns output hold from address change t oh 5 10 ns ac characteristics write cycle (t a = -40 c to +85 c; v cc = 5v 10%) ds2016-100 DS2016-150 parameter symbol min typ max min typ max units notes write cycle time t wc 100 150 ns write pulse width t wp 75 120 ns address setup time t aw 0 0 ns write recovery time t wr 10 10 ns output high-z from we t odw 35 70 ns output active from we t oew 5 5 ns data setup time t ds 40 60 ns data hold time t dh 0 0 ns data retention characteristics (t a = -40 c to +85 c) parameter symbol conditions min typ max units data retention supply voltage v dr ce 3 v cc - 0.5v 2.0 5.5 v data retention current at 5.5v i ccr1 ce 3 v cc - 0.5v 0.1* 1 a data retention current at 2.0v i ccr2 ce 3 v cc - 0.5v 50* 750 na chip deselect to data retention t cdr 0 s recovery time t r 2 ms * typical values are at 25c
ds2016 4 of 9 +3-volt operation recommended dc operating conditions (t a = -40 c to +85 c) parameter symbol min typ max units notes power supply voltage v cc 2.7 3.0 3.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.3 0.6 v data retention voltage v dr 2.0 3.5 v dc characteristics (t a = -40 c to +85 c; v cc = 2.7v to 3.5v) parameter symbol conditions min typ max units input leakage current i il 0v v in v cc 0.1 a i/o leakage current i lo ce =v ih , 0v v io v cc 0.5 a output high current i oh v oh = 2.2v -0.5 ma output low current i ol v ol = 0.4v 4.0 ma standby current i ccs1 ce = 2.0v 0.1 ma standby current i ccs2 ce 3 v cc -0.3v t a =60c 500 na standby current i ccs2 ce 3 v cc -0.3v t a =25c 50 na operating current i cco ce =0.6v min cycle 25 ma ac characteristics read cycle (t a = -40 c to +85 c; v cc = 2.7v to 3.5v) parameter symbol min typ max units notes read cycle time t rc 250 ns access time t acc 250 ns oe to output valid t oe 120 ns ce to output valid t co 250 ns ce or oe to output active t coe 15 ns output high-z from deselection t od 5 100 ns output hold from address change t oh 15 ns
ds2016 5 of 9 ac characteristics write cycle (t a = -40c to +85c; v cc = 2.7v to 3.5v) parameter symbol min typ max units notes write cycle time t wc 250 ns write pulse width t wp 190 ns address setup time t aw 0 ns write recovery time t wr 25 ns output high-z from we t odw 90 ns output active from we t oew 5 ns data setup time t ds 100 ns data hold time t dh 0 ns data retention characteristics (t a = -40c to +85c) parameter symbol conditions min typ max units data retention supply voltage v dr ce 3 v cc - 0.3v 2.0 3.5 v data retention current at 3.5v i ccr1 ce 3 v cc - 0.3v 50* 1000 na data retention current at 2.0v i ccr2 ce 3 v cc - 0.3v 50* 750 na chip deselect to data retention t cdr 0 s recovery time t r 2 ms * typical values are at 25c timing diagram: read cycle see note 1
ds2016 6 of 9 timing diagram: write cycle 1 see notes 2, 3, 4, 5, 6 and 7 timing diagram: write cycle 2 see notes 2, 3, 4, 5, 6 and 7
ds2016 7 of 9 timing diagram: data retention - power-up, power-down figure 1 see note 8 notes: 1. we is high for read cycles. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh and t ds are measured from the earlier of ce or we going high. 5. if the ce low transition occurs simultaneously with or later than the we low transition, the output buffers remain in a high impedance state. 6. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state. 7. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state. 8. if the v ih level of ce is 2.0v during the period that v cc voltage is going down from 4.5v to 2.7v, i ccs1 current flows. 9. the ds2016 maintains full operation from 5.5v to 2.7v. the electrical characteristics tables show two tested and guaranteed points of operation. for operation between 4.5v and 3.5 volts, use the composite worst case characteristics from both 5v and 3v operation for design purposes. dc test conditions outputs open all voltages are referenced to ground. ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0v - 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns
ds2016 8 of 9 ds2016 24-pin dip pkg 24-pin dim min max a in. mm 1.245 31.62 1.270 32.25 b in. mm 0.530 13.46 0.550 13.97 c in. mm 0.140 3.56 0.160 4.06 d in. mm 0.600 15.24 0.625 15.88 e in. mm 0.015 0.380 0.050 1.27 f in. mm 0.120 3.05 0.145 3.68 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.625 15.88 0.675 17.15 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.022 0.56
ds2016 9 of 9 ds2016s 24-pin soic pkg 24-pin dim min max a in. mm 0.094 2.38 0.105 2.68 a1 in. mm 0.004 0.102 0.012 0.30 b in. mm 0.013 0.33 0.020 0.51 c in. mm 0.009 0.229 0.013 0.33 d in. mm 0.598 15.19 0.612 15.54 e in. mm 0.050 bsc 1.27 bsc e1 in. mm 0.290 7.37 0.300 7.62 h in. mm 0.398 10.11 0.416 10.57 l in. mm 0.016 0.40 0.040 1.02 a 0 8 the chamfer on the body is optional. if it is not present, a terminal 1 identifier must be positioned so that ? or more of its area is contained in the hatched zone.
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